Non-volatile memory (NVM) circuits have achieved widespread adoptions for code and data storage applications. An important aspect of NVM circuits is their performance, which includes endurance (number of programming or write/erase cycles) and data retention after write/erase cycling and erase speed. Within the industry, the performance of NVM technology has been characterized extensively. Generally, the NVM circuits should be able to endure over 100 thousand to 1 million programming cycles with data retention exceeding 20 years, even at extreme ambient temperatures.
One type of NVM circuits is a silicon-oxide-nitride-oxide-silicon (SONOS) NVM circuit. In SONOS types of NVM circuits, memory operations, such as programming and erasing involve charging and discharging electrons from a nitride layer of an oxide-nitride-oxide dielectric stack. The charging and discharging of electron charge is achieved by, for example, Fowler-Nordheim (FN) tunneling and/or hot electron injection (HCl).
The thickness of the various layers of the dielectric stack is important as they affect programming and erase speeds. For example, a thicker storage layer results in slow erase speed while a thinner storage layer results in slow programming speed. This can impact yield due to small operating window. The thickness of the other layers as well as the overall thickness of the storage stack also affect the performance and reliability of the memory cell. For example, thinner dielectric layer and bottom oxide increases erase speed, but may cause data retention problems. Tight control of the thickness of the different layers is therefore important for performance and reliability of NVM circuits.